34 lines
594 B
Verilog
34 lines
594 B
Verilog
/* pr1636409 */
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module top;
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wire [3:0] fail, good;
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wire eni;
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reg [2:0] rg;
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reg in, en, clk;
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assign #1 eni = en;
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assign #1 fail = (eni) ? {rg,in} : 'b0;
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assign #1 good = {4{eni}} & {rg,in};
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always @(fail or good or eni) begin
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$strobe("fail=%b, good=%b, en=%b at %0t", fail, good, eni, $time);
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end
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always #10 clk = ~clk;
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always @(posedge clk) begin
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en = ~en;
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in = ~in;
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rg = ~rg;
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end
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initial begin
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// $dumpfile("results.vcd");
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// $dumpvars(0, top);
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clk = 0;
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en = 0;
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in = 0;
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rg = 3'b101;
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#50 $finish(0);
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end
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endmodule
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