62 lines
1.1 KiB
Verilog
62 lines
1.1 KiB
Verilog
// `define READ read_good
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module top;
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reg clk;
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reg dout;
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reg [7:0] data;
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integer lp;
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always #10 clk = ~clk; // Build a clock generator.
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always @(negedge clk) dout = ~dout; // Build a bit stream.
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initial begin
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clk = 0;
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dout = 0;
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@(negedge clk);
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for (lp=0; lp<4; lp=lp+1) begin
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#0 read_bad(data);
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$display("Read(%0d) %b from the bit stream.", lp, data);
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#20; // For the fun of it skip a clock.
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end
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#1 $finish(0);
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end
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// This one locks up on the third call.
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task read_bad;
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output [7:0] edata;
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integer i;
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reg [7:0] rddata;
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begin
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for(i=7; i>=0; i=i-1) begin
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@(posedge clk);
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$display(" Reading bit %0d", i);
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rddata[i] = dout; // <<--- This appears to be the problem line!
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end
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assign edata = rddata;
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end
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endtask
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// This one works fine.
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task read_good;
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output [7:0] edata;
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integer i;
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reg [7:0] edata;
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begin
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for(i=7; i>=0; i=i-1) begin
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@(posedge clk);
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$display(" Reading bit %0d", i);
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edata[i] = dout;
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end
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end
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endtask
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endmodule
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