66 lines
779 B
Verilog
66 lines
779 B
Verilog
/* pr1623097 */
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`timescale 1ns/1ns
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module top;
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reg [3:0] state;
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reg [3:0] data;
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reg [3:0] clear;
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reg clk;
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genvar i;
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initial begin
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#0; // avoid time-0 race
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clk = 0; data = 4'b1111; clear = 4'b1111;
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$monitor($time,,"clk=%b, data=%b, clear=%b, state=%b",
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clk, data, clear, state);
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#10 clear = 4'b0000;
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#10 clk = 1;
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#10 clk = 0; clear = 4'b0010;
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#10 clear = 4'b0000; data = 4'b1010;
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#10 clk = 1;
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#10 clk = 0;
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end
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// This fails!
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generate for (i=0; i<4; i=i+1) begin:sm
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always @(posedge clk or posedge clear[i]) begin
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if (clear[i]) state[i] <= 1'b0; // Async. clear the flip bit.
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else begin
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state[i] <= #1 data[i];
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end
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end
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end endgenerate
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endmodule
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