26 lines
530 B
Verilog
26 lines
530 B
Verilog
module x;
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parameter bar0_low = 5'd16; // Register Space
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reg [31:bar0_low] base_address0;
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reg [31:0] ad_in_d;
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wire [0:5] hit_bar;
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wire a = |bar0_low;
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wire [31:0] e = ad_in_d[31:bar0_low];
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wire b = (base_address0==e);
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wire d = b;
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assign hit_bar[0] = a ? d : 0;
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initial begin
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if ($bits(base_address0) != 16) begin
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$display("FAILED -- $bits(base_address0) = %0d", $bits(base_address0));
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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