48 lines
903 B
Verilog
48 lines
903 B
Verilog
module test;
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reg [1:0] bus;
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reg [1:0] skewed_bus;
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integer delay0; initial delay0 = 5;
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integer delay1; initial delay1 = 10;
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/* attempt to model skew across the bus using transport delays */
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always @( bus[0] )
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begin
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skewed_bus[0] <= #delay0 bus[0];
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end
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always @( bus[1] )
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begin
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skewed_bus[1] <= #delay1 bus[1];
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end
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initial begin
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#1 bus = 2'b00;
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#11 if (skewed_bus !== 2'b00) begin
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$display("FAILED -- setup failed.");
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$finish;
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end
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bus = 2'b11;
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#4 if (skewed_bus !== 2'b00) begin
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$display("FAILED -- changed far too soon");
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$finish;
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end
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#2 if (skewed_bus !== 2'b01) begin
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$display("FAILED -- partial change not right.");
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$finish;
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end
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#5 if (skewed_bus !== 2'b11) begin
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$display("FAILED -- final change not right");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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