38 lines
745 B
Verilog
38 lines
745 B
Verilog
module test ();
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reg [2:0] in;
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wire Oand, Oor;
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dut #(.is_and(1)) dand (.O(Oand), .A(in[1]), .B(in[0]));
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dut #(.is_and(0)) dor (.O(Oor ), .A(in[1]), .B(in[0]));
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initial begin
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for (in = 0 ; in < 4 ; in = in+1) begin
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#1 /* settle time. */ ;
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if (Oand !== &in[1:0]) begin
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$display("FAILED -- in=%b, Oand=%b", in, Oand);
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$finish;
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end
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if (Oor !== |in[1:0]) begin
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$display("FAILED -- in=%b, Oor=%b", in, Oor);
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$finish;
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end
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end // for (in = 0 ; in < 4 ; in = in+1)
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$display("PASSED");
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end
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endmodule
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module dut (output O, input A, input B);
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parameter is_and = 1;
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generate
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if (is_and)
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and g(O, A, B);
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else
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or g(O, A, B);
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endgenerate
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endmodule // dut
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