28 lines
503 B
Verilog
28 lines
503 B
Verilog
module main;
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real rval;
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wire [63:0] wbits = $realtobits(rval);
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reg [63:0] rbits;
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initial begin
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rval = 1.5;
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rbits = $realtobits(rval);
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#1 /* Let the wbits value propagate */ ;
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if (rbits !== 64'h3ff80000_00000000) begin
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$display("FAILED -- rbits=%h", rbits);
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$finish;
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end
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if (wbits !== rbits) begin
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$display("FAILED -- rval=%f, rbits=%h, wbits=%h", rval, rbits, wbits);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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