47 lines
778 B
Verilog
47 lines
778 B
Verilog
`begin_keywords "1364-2005"
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module main;
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wire [1:0] di;
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reg [1:0] do;
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reg dir;
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wire [1:0] q;
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sub dut(.Q({q[0],q[1]}), .Di(di), .Do(do), .dir(dir));
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initial begin
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dir = 0;
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do = 2'b10;
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#1 if (q !== 2'bzz) begin
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$display("FAILED -- q=%b, dir=%b", q, dir);
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$finish;
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end
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dir = 1;
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#1 if (q !== 2'b01) begin
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$display("FAILED -- q=%b, dir=%b, do=%b", q, dir, do);
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$finish;
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end
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if (di !== 2'b10) begin
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$display("FAILED -- di=%b, dir=%b, do=%b", di, dir, do);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module sub(inout [1:0]Q,
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output[1:0]Di,
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input [1:0]Do,
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input dir);
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assign Di = Q;
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assign Q = dir? Do : 2'bzz;
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endmodule // sub
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`end_keywords
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