23 lines
358 B
Verilog
23 lines
358 B
Verilog
module test;
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wire [3:0] a;
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reg [1:0] b;
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assign a[0+:2] = b;
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assign a[3-:2] = b;
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initial begin
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b = 2'b01;
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#1 if (a !== 4'b0101) begin
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$display("FAILED -- b=%b, a=%b", b, a);
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$finish;
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end
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b=2'b10;
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#1 if (a !== 4'b1010) begin
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$display("FAILED -- b=%b, a=%b", b, a);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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