67 lines
1.5 KiB
Verilog
67 lines
1.5 KiB
Verilog
module bts ( z , a , e);
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inout z ; wire z ;
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input a ; wire a ;
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input e ; wire e ;
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assign #4 z= ( (e==1'b1)? a : 1'bz );
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endmodule
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module test();
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reg [1:0] aa;
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wire [1:0] zz;
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reg [1:0] ee;
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bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1]));
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bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0]));
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initial begin
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// $dumpvars;
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ee=2'b00;
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aa=2'b00; #100;
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if (zz !== 2'bzz) begin
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$display("FAILED -- (1) All disabled, expected HiZ, got %b", zz);
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$finish;
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end
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aa=2'b11; #100;
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if (zz !== 2'bzz) begin
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$display("FAILED -- (2) All disabled, expected HiZ, got %b", zz);
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$finish;
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end
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aa=2'b00; #100;
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if (zz !== 2'bzz) begin
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$display("FAILED -- (3) All disabled, expected HiZ, got %b", zz);
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$finish;
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end
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aa=2'b11; #100;
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if (zz !== 2'bzz) begin
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$display("FAILED -- (4) All disabled, expected HiZ, got %b", zz);
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$finish;
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end
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ee=2'b11;
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aa=2'b00; #100;
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if (zz !== 2'b00) begin
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$display("FAILED -- (5) All enabled, expected 00, got %b", zz);
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$finish;
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end
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aa=2'b11; #100;
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if (zz !== 2'b11) begin
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$display("FAILED -- (6) All enabled, expected 11, got %b", zz);
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$finish;
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end
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aa=2'b00; #100;
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if (zz !== 2'b00) begin
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$display("FAILED -- (7) All enabled, expected 00, got %b", zz);
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$finish;
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end
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aa=2'b11; #100;
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if (zz !== 2'b11) begin
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$display("FAILED -- (8) All enabled, expected 11, got %b", zz);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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