32 lines
611 B
Verilog
32 lines
611 B
Verilog
/*
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* This is the essence of tracker id#1421777. The problem is the error
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* message around the "... dut.tmp" expression. This probram won't
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* compile while the reported bug still lives.
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*/
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module main;
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reg b;
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wire a;
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// The a.tmp is valid, but tricky because it is an implicit wire.
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wire foo = dut.tmp;
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X dut(a, b);
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initial begin
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b = 0;
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#1 $display("a=%b, tmp=%b", a, foo);
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if (a !== foo) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module X(output a, input b);
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not (tmp, b);
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buf(a, tmp);
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endmodule // X
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