62 lines
1.5 KiB
Verilog
62 lines
1.5 KiB
Verilog
//
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// Copyright (c) 2001 Ed Schwartz (schwartz@r11.ricoh.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Verify PR142 - Added something to print PASSED..
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module testit;
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reg clk;
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reg [2:0] cnt;
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always
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begin
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# 50 clk = ~clk;
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end // always begin
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task idle;
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input [15:0] waitcnt;
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begin: idletask
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// begin
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integer i;
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for (i=0; i < waitcnt; i = i + 1)
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begin
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@ (posedge clk);
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end // for (i=0; i < waitcnt; i = i + 1)
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end
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endtask // idle
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initial begin
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clk = 0;
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cnt = 0;
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$display ("One");
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cnt = cnt + 1;
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idle(3);
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cnt = cnt + 1;
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$display ("Two");
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if(cnt === 2)
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$display("PASSED");
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else
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$display("FAILED");
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$finish;
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end
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endmodule
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