62 lines
1.1 KiB
Verilog
62 lines
1.1 KiB
Verilog
module main;
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parameter use_wid = 4;
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reg [use_wid-1:0] d;
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wire [use_wid-1:0] q;
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reg clk;
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defparam dut.wid = use_wid;
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B dut (.Q(q), .D(d), .C(clk));
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initial begin
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clk = 0;
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d = 4'b0000;
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#1 clk = 1;
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#1 clk = 0;
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if (q !== 4'b0000) begin
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$display("FAILED -- d=%b, q=%b", d, q);
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$finish;
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end
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d = 4'b1111;
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#1 clk = 1;
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#1 clk = 0;
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if (q !== 4'b1111) begin
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$display("FAILED -- d=%b, q=%b", d, q);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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/*
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* although the wid paramter is default to 3 in this module, the point
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* of this test is to have the instantiating module (main) give a
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* different value and have that value properly handlued in all the
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* situations of this module.
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*/
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module B
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#(parameter wid = 3)
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(output [wid-1:0] Q,
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input [wid-1:0] D,
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input C);
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// the override from main will cause this to be a width of 4.
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prim U [wid-1:0] (Q, D, C);
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//prim U [wid-1:0] (.Q(Q), .D(D), .C(C));
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endmodule // B
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module prim(output reg Q, input D, C);
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always @(posedge C)
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Q <= D;
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endmodule // prim
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