67 lines
1.1 KiB
Verilog
67 lines
1.1 KiB
Verilog
//**************************************************************************
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module COUNTER(CLOCK_I, nARST_I, COUNT_O);
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parameter CBITS = 3;
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input CLOCK_I;
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input nARST_I;
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output[CBITS-1:0] COUNT_O;
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reg[CBITS-1:0] COUNT_O;
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always @(posedge CLOCK_I or negedge nARST_I)
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if(nARST_I==1'b0)
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COUNT_O <= {CBITS{1'b0}};
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else
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COUNT_O <= COUNT_O + 1;
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endmodule
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//--------------------------------------------------------------------------
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module MULTIPLE_COUNTERS(CLOCK_I, nARST_I, COUNT_O);
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parameter M = 3;
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parameter CBITS = 4;
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input CLOCK_I;
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input nARST_I;
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output[M*CBITS-1:0] COUNT_O;
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COUNTER #(.CBITS(CBITS)) INST_COUNTER[M-1:0] (CLOCK_I, nARST_I, COUNT_O);
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endmodule
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//--------------------------------------------------------------------------
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module TEST_COUNTER;
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parameter M = 2;
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parameter CBITS = 2;
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reg CLOCK;
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reg nARST;
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reg CTRL_I;
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wire[M*CBITS-1:0] COUNTS;
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MULTIPLE_COUNTERS #(.M(M),
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.CBITS(CBITS)) INST_MCTR(CLOCK, nARST, COUNTS);
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initial CLOCK=1;
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always #5 CLOCK=~CLOCK;
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initial
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begin
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nARST=1;
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#5 nARST=0;
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#5 nARST=1;
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#200 $display("PASSED");
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$finish;
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end
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endmodule
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