43 lines
559 B
Verilog
43 lines
559 B
Verilog
`begin_keywords "1364-2005"
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/*
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* This program is based on PR#1077.
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*
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* Expected output:
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* one
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* y = x
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* one
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* y = 1
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* one
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* y = 1
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*/
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module bool;
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reg clk,y;
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reg [31:0] count;
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initial clk=0;
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always #2.5 clk = ~clk;
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initial begin
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count = 'h8;
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#20
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$finish(0);
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end
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always @(posedge clk)
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begin
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// BUG: this should eval to "1" but does not!
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y <= count[10] || ~count[5:3];
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// this should print "one" and does
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if(count[10] || ~(count[5:3]))
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$display("one");
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else
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$display("zero");
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$display("y = %b",y);
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end
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endmodule
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`end_keywords
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