28 lines
678 B
Verilog
28 lines
678 B
Verilog
module test_file;
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reg [64:1] file_name;
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initial begin
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file_name = 64'h4242434442424344;
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end
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subtest1 subtest1(file_name);
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endmodule
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module subtest1(file_name);
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input [64:1] file_name;
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wire [64:1] file_name;
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integer outfile;
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initial #0 begin
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$display ("Execution started.");
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$display ("%s",file_name);
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// I don't know if the following line conforms to spec or not.
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outfile = $fopen({"work/",file_name});
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$display ("Execution finished.");
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$fdisplay (outfile, "Recorded data in %s",file_name);
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$fclose (outfile);
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$finish(0);
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end
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endmodule
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