73 lines
2.7 KiB
Verilog
73 lines
2.7 KiB
Verilog
/*
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* Test case showing the failure of the 'less than or equal' operator (note
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* that the 'greather than or equal' comparison also fails) on two signed
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* values. The 'foo' module defines inputs 'a' and 'b' as signed inputs,
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* then performs a LTE comparison of those two values in order to select the
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* smaller of the two as the result (via a mux). The generated output for
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* this test (via the display call) for icarus and a well known commercial
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* Verilog simulator are shown here. It is my belief that the commercial
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* simulator results reflect the correct behavior for a simulator.
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* Specifically, with signed numbers the value 32'h7fffffff represents the
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* maximum positive value while 32'h80000000 represents the minimum negative
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* value. Thus for Less Than or Equal comparison any negative value (ie
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* 32'h80000000) should evaluate to less than any positive value
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* (ie 32'h7fffffff). Note the difference in the last 4 comparisons between
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* the icarus results and the commercial results. The commercial results show
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* that the 32'h8000000? values are less than the 32'h7ffffff? values as is
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* expected.
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*
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* icarus commercial simulator
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* 7ffffff5 7ffffffa = 7ffffff5 # 7ffffff5 7ffffffa = 7ffffff5
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* 7ffffff6 7ffffffb = 7ffffff6 # 7ffffff6 7ffffffb = 7ffffff6
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* 7ffffff7 7ffffffc = 7ffffff7 # 7ffffff7 7ffffffc = 7ffffff7
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* 7ffffff8 7ffffffd = 7ffffff8 # 7ffffff8 7ffffffd = 7ffffff8
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* 7ffffff9 7ffffffe = 7ffffff9 # 7ffffff9 7ffffffe = 7ffffff9
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* 7ffffffa 7fffffff = 7ffffffa # 7ffffffa 7fffffff = 7ffffffa
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* 7ffffffb 80000000 = 7ffffffb # 7ffffffb 80000000 = 80000000
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* 7ffffffc 80000001 = 7ffffffc # 7ffffffc 80000001 = 80000001
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* 7ffffffd 80000002 = 7ffffffd # 7ffffffd 80000002 = 80000002
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* 7ffffffe 80000003 = 7ffffffe # 7ffffffe 80000003 = 80000003
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*
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* iverilog -version:
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* Icarus Verilog version 0.7 ($Name: $)
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*
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* Compilation
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* iverilog -o iverilog.out
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* vvp iverilog.out
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*/
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module test ();
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reg clk;
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reg [31:0] a_dat;
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reg [31:0] b_dat;
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wire [31:0] result;
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initial begin
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clk <= 0;
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a_dat <= 32'h7fffFFF5;
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b_dat <= 32'h7fffFFFA;
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#500 $finish(0);
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end
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always #25 clk <= ~clk;
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always @(posedge clk)
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begin
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a_dat <= a_dat + 1;
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b_dat <= b_dat + 1;
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$display("%x %x = %x", a_dat, b_dat, result);
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end
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foo foo_test(.a(a_dat), .b(b_dat), .RESULT(result));
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endmodule // test
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module foo(a, b, RESULT);
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input signed [31:0] a;
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input signed [31:0] b;
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output [31:0] RESULT;
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wire lessThanEqualTo;
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wire [31:0] mux;
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assign lessThanEqualTo=a<=b;
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assign mux=(lessThanEqualTo)?a:b;
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assign RESULT=mux;
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endmodule // foo
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