22 lines
364 B
Verilog
22 lines
364 B
Verilog
// based on PR#1022
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module foo;
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wire [-1:0] fred;
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assign fred = 1;
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initial begin
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#1 if (fred[0] !== 1) begin
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$display("FAILED -- fred[0] = %b", fred[0]);
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$finish;
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end
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if (fred[-1] !== 0) begin
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$display("FAILED -- fred[-1] = %b", fred[-1]);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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