30 lines
352 B
Verilog
30 lines
352 B
Verilog
/*
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* Based on PR#1008
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*/
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`timescale 1 ps / 1 ps
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module star;
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reg a;
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reg b;
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initial begin
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$monitor("b = %b", b);
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#1;
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a = 1;
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#2;
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a = 0;
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#2;
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a = 1;
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end
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/* This generated the error:
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:0: internal error: NetProc::nex_output not implemented
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Before CVS 20040630 */
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always @* begin
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b = #1 ~a;
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end
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endmodule // star
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