49 lines
1.1 KiB
Verilog
49 lines
1.1 KiB
Verilog
/***********************************************************************
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Incorrect direction non-detection test case
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Copyright (C) 2001 Eric LaForest, ecl@pet.dhs.org
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Licenced under GPL
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***********************************************************************/
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module CPU (data, address, rw, clock, reset);
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inout [15:0] data;
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output [15:0] address;
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// This should be an output really....
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input rw;
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input clock, reset;
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reg [15:0] data, address; // XXX error on data
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reg rw; // error on rw
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// I presume these should not be allowed to occur....
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always @(posedge clock) begin
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rw <= 1'b1;
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end
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always @(negedge clock) begin
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rw <= 1'b0;
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end
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endmodule
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module BENCH ();
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reg [15:0] address, data;
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reg rw, clock, reset;
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CPU fm (address, data, rw, clock, reset);
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initial begin
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clock <= 0;
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reset <= 1;
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#1000;
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$finish;
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end
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always begin
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# 10 clock <= ~clock;
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end
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endmodule
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