14 lines
330 B
Verilog
14 lines
330 B
Verilog
module main;
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string img;
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initial begin
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if (!$value$plusargs("img=%s", img)) begin
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$display("Specify image file with +img=<image>.");
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$finish_and_return(1);
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end
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$display("Using image: %s", img);
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if (img != "test_image.file") $display("FAILED");
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else $display("PASSED");
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end
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endmodule // main
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