33 lines
684 B
Verilog
33 lines
684 B
Verilog
module main;
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wire logic [3:0][7:0] foo;
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genvar idx;
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for (idx = 0 ; idx <= 3 ; idx = idx+1) begin: test
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test dut (.sum(foo[idx]), .a(idx));
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end
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logic [7:0] tmp;
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initial begin
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#0; // avoid time-zero race
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for (tmp = 0 ; tmp <= 3 ; tmp = tmp+1) begin
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//if ($bits(foo[tmp]) !== 8) begin
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// $display("FAILED -- $bits = %d", $bits(foo[tmp]));
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// $finish;
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//end
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if (foo[tmp] !== (tmp+8'd5)) begin
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$display("FAILED -- foo[%d] = %b", tmp, foo[tmp]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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module test (output logic[7:0] sum, input logic [7:0]a);
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assign sum = a + 8'd5;
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endmodule // test
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