76 lines
1.6 KiB
Verilog
76 lines
1.6 KiB
Verilog
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module test(input wire load, drain,
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input wire clk, data,
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output reg foo_nxt, bar_nxt);
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reg foo, bar;
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(* ivl_combinational *)
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always @* begin
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foo_nxt = foo;
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bar_nxt = bar;
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if (load) begin
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foo_nxt = data;
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bar_nxt = 1;
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end else if (drain) begin
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bar_nxt = 0;
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end
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end
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always @(posedge clk) begin
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foo <= foo_nxt;
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bar <= bar_nxt;
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end
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endmodule // test
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module main;
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reg clk, load, drain, data;
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wire foo, bar;
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test dut (.clk(clk), .load(load), .drain(drain), .data(data),
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.foo_nxt(foo), .bar_nxt(bar));
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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load = 1;
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drain = 0;
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data = 1;
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#1 clk = 1;
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#1 clk = 0;
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$display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
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$time, load, drain, data, foo, bar);
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if (foo !== 1 || bar !== 1) begin
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$display("FAILED -- foo=%b, bar=%b (1)", foo, bar);
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$finish;
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end
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data = 0;
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#1 clk = 1;
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#1 clk = 0;
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$display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
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$time, load, drain, data, foo, bar);
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if (foo !== 0 || bar !== 1) begin
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$display("FAILED -- foo=%b, bar=%b (2)", foo, bar);
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$finish;
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end
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load = 0;
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drain = 1;
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#1 ;
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if (foo !== 0 || bar !== 0) begin
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$display("FAILED -- foo=%b, bar=%b (3)", foo, bar);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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$display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
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$time, load, drain, data, foo, bar);
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$display("PASSED");
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end
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endmodule // main
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