16 lines
402 B
Verilog
16 lines
402 B
Verilog
module top;
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event my_event;
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// The following two line should be an error
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// You can not take the edge of a named event.
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always @(posedge my_event) $display("Posedge event.");
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always @(negedge my_event) $display("Negedge event.");
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// This should work correctly.
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always @(my_event) $display("Any event edge.");
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initial begin
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#1 ->my_event;
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#1 $display("FAILED");
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end
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endmodule
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