41 lines
771 B
Verilog
41 lines
771 B
Verilog
module main;
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reg [7:0] mem [7:0], D;
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reg [3:0] radr, wadr;
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reg wr, clk;
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/*
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* This implements the synchronous write port to the memory.
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*/
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always @(posedge clk)
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if (wr) mem[wadr] <= D;
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// This is the asynchronous read port from the memory.
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wire[7:0] Q = mem[radr];
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(* ivl_synthesis_off *)
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initial begin
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wr = 0;
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clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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for (wadr = 0 ; wadr < 8 ; wadr = wadr+1) begin
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wr = 1;
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D = { 2{wadr} };
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#1 clk = 1;
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#1 clk = 0;
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end
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wr = 0;
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for (radr = 0 ; radr < 8 ; radr = radr+1) begin
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#1 if (Q !== {2{radr}}) begin
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$display("FAILED -- mem[%d] == 'b%b", radr, Q);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule
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