60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: memidxrng.v,v 1.1 2001/09/29 05:03:41 sib4 Exp $
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// $Log: memidxrng.v,v $
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// Revision 1.1 2001/09/29 05:03:41 sib4
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// add memidxrng.v: memory address range check
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//
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module memidxrng;
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reg mem[12:2];
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reg [7:0] i;
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integer errs = 0;
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initial
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begin
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for (i=0; i<255; i=i+1) mem[i] <= ^i;
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#1;
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for (i=0; i<17; i=i+1)
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$display("mem[%d] = %b \%b", i, mem[i], ^i);
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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if (mem[13] !== 1'bx)
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begin
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$display("FAILED: mem[13] = %b, expect x", mem[14]);
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errs = errs + 1;
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end
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if (mem[1] !== 1'bx)
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begin
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$display("FAILED: mem[1] = %b, expect x", mem[1]);
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errs = errs + 1;
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end
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`endif
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if (errs===0)
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$display("PASSED");
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$finish;
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end
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endmodule
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