73 lines
1.9 KiB
Verilog
73 lines
1.9 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.will need a Picture Elements Binary Software
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This program demonstrates the mixing of reg and memories in l-value
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* contatenations.
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*/
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module main;
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reg [3:0] mem [2:0];
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reg a, b;
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initial begin
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mem[0] = 0;
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mem[1] = 0;
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mem[2] = 0;
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{b, mem[1], a} <= 6'b0_0000_1;
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#1
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if (a !== 1'b1) begin
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$display("FAILED -- a = %b", a);
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$finish;
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end
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if (mem[1] !== 4'b0000) begin
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$display("FAILED -- mem[1] = %b", mem[1]);
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$finish;
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end
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if (b !== 1'b0) begin
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$display("FAILED -- b = %b", b);
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$finish;
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end
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{b, mem[1], a} <= 6'b0_1111_0;
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#1
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if (a !== 1'b0) begin
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$display("FAILED -- a = %b", a);
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$finish;
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end
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if (mem[0] !== 4'b0000) begin
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$display("FAILED -- mem[0] - %b", mem[0]);
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$finish;
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end
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if (mem[1] !== 4'b1111) begin
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$display("FAILED -- mem[1] = %b", mem[1]);
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$finish;
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end
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if (b !== 1'b0) begin
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$display("FAILED -- b = %b", b);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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