124 lines
3.7 KiB
Verilog
124 lines
3.7 KiB
Verilog
module top;
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parameter le0 = 1'b0 <-> 1'b0; // 1'b1
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parameter le1 = 1'b0 <-> 1'b1; // 1'b0
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parameter le2 = 1'b0 <-> 1'bz; // 1'bx
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parameter le3 = 1'b0 <-> 1'bx; // 1'bx
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parameter le4 = 1'b1 <-> 1'b0; // 1'b0
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parameter le5 = 1'b1 <-> 1'b1; // 1'b1
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parameter le6 = 1'b1 <-> 1'bz; // 1'bx
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parameter le7 = 1'b1 <-> 1'bx; // 1'bx
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parameter le8 = 1'bz <-> 1'b0; // 1'bx
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parameter le9 = 1'bz <-> 1'b1; // 1'bx
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parameter lea = 1'bz <-> 1'bz; // 1'bx
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parameter leb = 1'bz <-> 1'bx; // 1'bx
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parameter lec = 1'bx <-> 1'b0; // 1'bx
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parameter led = 1'bx <-> 1'b1; // 1'bx
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parameter lee = 1'bx <-> 1'bz; // 1'bx
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parameter lef = 1'bx <-> 1'bx; // 1'bx
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parameter [1:0] lew = 4'b0110 <-> 4'b1001; // 2'b01
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parameter [1:0] lews = $signed(4'b0110 <-> 4'b1001); // 2'b11
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parameter ler0 = 0.0 <-> 1'b0; // 1'b1
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parameter ler1 = 1'b0 <-> 2.0; // 1'b0
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parameter ler2 = 2.0 <-> 1'bx; // 1'bx
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parameter ler3 = -5.0 <-> 2.0; // 1'b1
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reg pass;
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initial begin
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pass = 1'b1;
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if (le0 !== 1'b1) begin
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$display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", le0);
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pass = 1'b0;
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end
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if (le1 !== 1'b0) begin
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$display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", le1);
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pass = 1'b0;
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end
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if (le2 !== 1'bx) begin
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$display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", le2);
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pass = 1'b0;
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end
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if (le3 !== 1'bx) begin
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$display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", le3);
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pass = 1'b0;
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end
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if (le4 !== 1'b0) begin
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$display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", le4);
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pass = 1'b0;
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end
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if (le5 !== 1'b1) begin
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$display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", le5);
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pass = 1'b0;
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end
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if (le6 !== 1'bx) begin
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$display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", le6);
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pass = 1'b0;
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end
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if (le7 !== 1'bx) begin
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$display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", le7);
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pass = 1'b0;
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end
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if (le8 !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", le8);
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pass = 1'b0;
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end
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if (le9 !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", le9);
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pass = 1'b0;
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end
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if (lea !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", lea);
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pass = 1'b0;
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end
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if (leb !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", leb);
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pass = 1'b0;
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end
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if (lec !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", lec);
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pass = 1'b0;
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end
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if (led !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", led);
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pass = 1'b0;
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end
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if (lee !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", lee);
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pass = 1'b0;
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end
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if (lef !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", lef);
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pass = 1'b0;
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end
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if (ler0 !== 1'b1) begin
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$display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", ler0);
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pass = 1'b0;
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end
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if (ler1 !== 1'b0) begin
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$display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b1", ler1);
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pass = 1'b0;
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end
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if (ler2 !== 1'bx) begin
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$display("FAILED: 2.0 <-> 1'bx returned %b not 1'b1", ler2);
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pass = 1'b0;
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end
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if (ler3 !== 1'b1) begin
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$display("FAILED: -5.0 <-> 2.0 returned %b not 1'b1", ler3);
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pass = 1'b0;
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end
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if (lew !== 2'b01) begin
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$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", lew);
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pass = 1'b0;
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end
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if (lews !== 2'b11) begin
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$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", lews);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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