77 lines
1.5 KiB
Verilog
77 lines
1.5 KiB
Verilog
module main;
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int unsigned foo, bar = 10;
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int signed foos, bars = 10;
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int unsigned wire_sum;
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int wire_sums;
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assign wire_sum = foo + bar;
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assign wire_sums = foos + bars;
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function int unsigned sum(input int unsigned a, b);
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sum = a + b;
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endfunction
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function int unsigned sums(input int signed a, b);
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sums = a + b;
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endfunction
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initial begin
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foo = 9;
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$display("%0d * %0d = %0d", foo, bar, foo * bar);
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$display("sum(%0d,%0d) = %0d", foo, bar, sum(foo,bar));
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if (foo !== 9 || bar !== 10) begin
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$display("FAILED");
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$finish;
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end
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if (foo*bar !== 90) begin
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$display("FAILED");
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$finish;
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end
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if (sum(foo,bar) !== 19) begin
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$display("FAILED");
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$finish;
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end
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foos = -7;
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$display("%0d * %0d = %0d", foos, bars, foos * bars);
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$display("sums(%0d,%0d) = %0d", foos, bars, sums(foos,bars));
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if (foos !== -7 || bars !== 10) begin
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$display("FAILED");
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$finish;
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end
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if (foos*bars !== -70) begin
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$display("FAILED");
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$finish;
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end
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if (sums(foos,bars) !== 3) begin
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$display("FAILED");
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$finish;
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end
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#0; // allow CAs to propagate
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$display("wire_sum = %0d", wire_sum);
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$display("wire_sums = %0d", wire_sums);
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if (wire_sum !== 19) begin
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$display("FAILED");
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$finish;
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end
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if (wire_sums !== 3) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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