46 lines
786 B
Verilog
46 lines
786 B
Verilog
module main;
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wire [31:0] DB;
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reg E;
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X2 U (.DB(DB[31:8]), .E(E));
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Y1 V (.DB(DB[7:0]), .E(E));
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initial begin
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E = 0;
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#1 if (DB !== 32'hzzzzzzzz) begin
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$display("FAILED -- DB=%b", DB);
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$finish;
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end
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E = 1;
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#1 if (DB !== 32'h9zzzzz87) begin
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$display("FAILED -- DB=%b", DB);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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module X2(inout wire [31:8] DB, input wire E);
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X1 uu (.DB(DB[31:28]), .E(E));
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endmodule // X2
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module X1(inout wire [31:28] DB, input wire E);
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wire foo = DB[31:28];
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assign DB[31:28] = E? 4'b1001 : 4'bzzzz;
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endmodule // sub
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module Y1(inout wire [7:0] DB, input wire E);
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wire foo = DB[7:0];
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assign DB[7:0] = E? 8'h87 : 8'hzz;
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endmodule // sub
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