37 lines
541 B
Verilog
37 lines
541 B
Verilog
module main;
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wire qh = 1'bz;
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wire [1:0] Q;
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reg [2:0] D;
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buft a({qh,Q}, D);
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reg x;
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//assign D[0] = x;
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initial begin
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D = 3'bzz0;
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#1 $display("Q=%b, D=%b", Q, D);
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if (Q !== 2'bz0) begin
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$display("FAILED");
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$finish;
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end
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D[0] = 1;
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#1 $display("Q=%b, D=%b", Q, D);
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if (Q !== 2'bz1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module buft(inout [2:0] T, input [2:0] D);
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assign T = D;
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endmodule // buft
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