45 lines
899 B
Verilog
45 lines
899 B
Verilog
/*
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* This test deminstrates a complication in the handling of a vector
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* as a unit, instead of breaking it out. The problem is with the
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* legal inout expression that takes one bit of the vector. That
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* leads to a driver to the input of a part select, and also the
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* other way around. Yikes.
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*/
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module main;
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reg [1:0] drv = 2'b0z;
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wire [1:0] a = drv;
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reg en;
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bi dut0(a[0], en);
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initial begin
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en <= 0;
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#1 $display("drv=%b en=%b, a=%b (should be 0z)", drv, en, a);
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if (a !== 2'b0z) begin
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$display("FAILED");
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$finish;
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end
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en <= 1;
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#1 $display("drv=%b en=%b, a=%b (should be 01)", drv, en, a);
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if (a !== 2'b01) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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module bi (inout a, input en);
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reg val = 1;
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assign a = en? val : 1'bz;
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endmodule // bi
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