100 lines
2.6 KiB
Verilog
100 lines
2.6 KiB
Verilog
//
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// Copyright (c) 1999 Stephen Williams (steve@icarus.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// Test the divide (/) operator
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module top () ;
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reg [7:0] a, b, result;
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wire [7:0] wa, wb, wresult;
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assign wa = a;
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assign wb = b;
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assign wresult = wa / wb;
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always @(a or b)
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result = a / b;
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initial begin
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#1 a = 0; b = 1;
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# 1;
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if( result !== 8'b0)
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begin
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$display("FAILED - Divide 0/1 reg assign failed - is %b",result);
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$finish;
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end
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if( wresult !== 8'b0)
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begin
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$display("FAILED - Divide 0/1 wire assign failed - is %b",wresult);
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$finish;
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end
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#1 a = 1;
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#1 if( result !== 8'b1)
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begin
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$display("FAILED - Divide 1/1 reg assign failed - is %b",result);
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$finish;
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end
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if( wresult !== 8'b1)
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begin
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$display("FAILED - Divide 1/1 wire assign failed - is %b",wresult);
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$finish;
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end
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#1 a = 5; b = 2;
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#1 if( result !== 8'd2)
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begin
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$display("FAILED - Divide 5/2 reg assign failed - is %b",result);
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$finish;
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end
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if( wresult !== 8'd2)
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begin
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$display("FAILED - Divide 5/2 wire assign failed - is %b",wresult);
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$finish;
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end
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#1 a = 8'd255; b = 5;
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#1 if( result !== 51)
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begin
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$display("FAILED - Divide 255/5 reg assign failed - is %b",result);
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$finish;
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end
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if( wresult !== 51)
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begin
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$display("FAILED - Divide 255/5 wire assign failed - is %b",wresult);
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$finish;
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end
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#1 a = 1'bx; b = 3;
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#1 if( result !== 8'bxxxx_xxxx)
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begin
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$display("FAILED - Divide x/3 reg assign failed - is %b",result);
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$finish;
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end
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if( wresult !== 8'bxxxx_xxxx)
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begin
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$display("FAILED - Divide x/3 wire assign failed - is %b",wresult);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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