65 lines
1.7 KiB
Verilog
65 lines
1.7 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate function called from within function
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module main ();
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reg [31:0] val1,val2 ;
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reg error;
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function [31:0] myfunc2 ;
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input [31:0] in2 ;
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myfunc2 = in2;
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endfunction
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function [31:0] myfunc1 ;
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input [31:0] in1 ;
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myfunc1 = myfunc2(in1) ;
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endfunction
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initial
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begin
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error = 0;
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val1 = myfunc1(32'h0) ;
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if(val1 != 32'h0)
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begin
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$display("FAILED - function3.11C - function called from funct(1)");
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error = 1;
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end
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val2 = 32'h12345678 ;
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val1 = myfunc1(val2);
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if(val1 != val2)
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begin
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$display("FAILED - function3.11C - function called from funct(2)");
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error = 1;
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end
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if(myfunc1(32'h10101010) != 32'h10101010)
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begin
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$display("FAILED - function3.11C - function called from funct(3)");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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