28 lines
492 B
Verilog
28 lines
492 B
Verilog
/*
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* P1800/D8 22.13
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* "`__FILE__ expands to the name of the current input file, in the form of a
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* string literal."
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*/
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module aaa;
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initial begin
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#1;
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$display(`__FILE__);
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end
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endmodule
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/*
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* P1800/D8 22.13
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* "`__LINE__ expands to the current input line number, in the form of
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* a simple decimal number."
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*/
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module bbb;
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initial begin
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#2;
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if(`__LINE__ !== 21 ||
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`__LINE__ !== 22) begin
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$display("FAIL"); $finish;
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end
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$display("PASSED");
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end
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endmodule
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