45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
/* Copyright (C) 2000 Stephen G. Tell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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/* fdisplay1 - test $fwrite and $fdisplay system tasks without using $fopen
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*
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* NB: this may need a little tweaking, as I'm not sure that all verilogs
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* have the predefined $fdisplay descriptors 2 and 3 matching what
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* vpi_mcd_printf provides.
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*/
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module fdisplay1;
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integer fp;
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reg [7:0] a;
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initial begin
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$display("message to stdout (from $display)\n");
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$fwrite(1, "another message (via fwrite) ");
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$fdisplay(1,"to stdout\n (via fdisplay)");
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#5
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a = 8'h5a;
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$fwrite(1, "a = %b at %0t\n", a, $time);
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$finish(0);
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end // initial begin
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endmodule
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