62 lines
572 B
Verilog
62 lines
572 B
Verilog
module et1;
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reg [31:0] a;
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reg [31:0] b;
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wire [31:0] x;
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reg [31:0] y;
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event e1;
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initial begin
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// $dumpvars;
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$monitor ("T=", $time, ", a=", a, ", b=", b, ", x=",
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x, ", y=", y);
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#200
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$finish(0);
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end
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initial begin
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a = 10;
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b = 20;
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#10
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a = 30;
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#10
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b = 40;
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#10
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a = 50;
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-> et1.m1.e2;
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#10
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b = 60;
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-> et1.m1.e2;
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#10
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a = 70;
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-> et1.m1.e2;
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b = 80;
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#10
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a = 90;
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end
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always @e1 begin
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y <= b;
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end
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m m1 (a,x);
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endmodule
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module m (a,x);
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input [31:0] a;
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output [31:0] x;
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reg [31:0] x;
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event e2;
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always @e2 begin
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#1
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x <= a;
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#2
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-> et1.e1;
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end
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endmodule
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