53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
module test;
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// Test declaring the enum as a 3-bit logic.
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enum reg [2:0] { rstate[8] } reg_enum;
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enum bit [2:0] { bstate[8] } bit_enum;
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enum logic [2:0] { lstate[8] } log_enum;
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initial begin
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if ($bits(reg_enum) != 3) begin
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$display("FAILED -- $bits(reg_enum) == %0d", $bits(reg_enum));
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$finish;
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end
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if ($bits(bit_enum) != 3) begin
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$display("FAILED -- $bits(bit_enum) == %0d", $bits(bit_enum));
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$finish;
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end
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if ($bits(log_enum) != 3) begin
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$display("FAILED -- $bits(log_enum) == %0d", $bits(log_enum));
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$finish;
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end
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if ($bits(rstate0) != 3) begin
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$display("FAILED -- $bits(rstate0) == %0d", $bits(rstate0));
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$finish;
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end
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if ($bits(bstate0) != 3) begin
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$display("FAILED -- $bits(bstate0) == %0d", $bits(bstate0));
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$finish;
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end
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if ($bits(lstate0) != 3) begin
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$display("FAILED -- $bits(lstate0) == %0d", $bits(lstate0));
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$finish;
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end
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if (rstate0 !== 3'b000 || bstate0 !== 3'b000 || lstate0 !== 3'b000) begin
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$display("FAILED -- rstate0 == %b", rstate0);
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$finish;
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end
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if (rstate4 !== 3'b100 || bstate4 !== 3'b100 || lstate4 !== 3'b100) begin
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$display("FAILED -- rstate4 == %b", rstate4);
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$finish;
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end
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if (rstate7 !== 3'b111 || bstate7 !== 3'b111 || lstate7 !== 3'b111) begin
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$display("FAILED -- rstate7 == %b", rstate7);
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$finish;
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end
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$display ("PASSED");
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end
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endmodule // test
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