67 lines
1.7 KiB
Verilog
67 lines
1.7 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: eeq.v,v 1.1 2001/06/26 01:07:15 sib4 Exp $
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// $Log: eeq.v,v $
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// Revision 1.1 2001/06/26 01:07:15 sib4
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// new test for === and !==
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//
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//
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// Test for === amd !== in structural context.
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module eeq;
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reg [3:0] a, b;
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wire eeq = a === b;
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`ifdef DONT_TEST_NEE
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wire nee = ~(a === b);
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`else
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wire nee = a !== b;
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`endif
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reg err;
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always
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begin
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#2;
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$display("%b %b ===%b !==%b", a, b, eeq, nee);
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if (((a === b) !== eeq) || ((a !== b) !== nee)) err = 1;
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end
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initial
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begin
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err = 0;
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#1 a = 4'b zx10; b = 4'b zx10; #1;
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#1 a = 4'b 1x10; b = 4'b zx10; #1;
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#1 a = 4'b xz10; b = 4'b zx10; #1;
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#1 a = 4'b xz01; b = 4'b zx10; #1;
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#1 a = 4'b 0000; b = 4'b 0000; #1;
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#1 a = 4'b 1111; b = 4'b 1111; #1;
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#1 a = 4'b xxxx; b = 4'b xxxx; #1;
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#1 a = 4'b zzzz; b = 4'b zzzz; #1;
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#1;
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if (err)
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$display("FAILED");
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else
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$display("PASSED");
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$finish;
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end
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endmodule
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