36 lines
937 B
Verilog
36 lines
937 B
Verilog
module top;
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reg passed;
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reg [4:1] result;
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initial begin
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passed = 1'b1;
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result = 4'b0000;
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// Fork some processes and wait for the one with the least delay to finish.
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fork
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#3 result[3] = 1'b1;
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#4 result[4] = 1'b1;
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join_none
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fork
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#1 result[1] = 1'b1;
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#2 result[2] = 1'b1;
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join_any
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// Disable the rest of the forked processes.
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disable fork;
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// Only the 1st bit should be set.
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if (result !== 4'b0001) begin
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$display("More than one process ran before the disable fork: %b", result);
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passed = 1'b0;
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result = 4'b0001;
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end
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// Wait to make sure the disabled processes do not run at a later time.
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#10;
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// Only the 1st bit should still be set.
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if (result !== 4'b0001) begin
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$display("Processes ran to completion after being disabled: %b", result);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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