64 lines
1.1 KiB
Verilog
64 lines
1.1 KiB
Verilog
module main;
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reg a, b, c;
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reg clk, rst, rnd;
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(* ivl_sinthesis_on *)
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always @(posedge clk or posedge rst)
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if (rst) begin
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a <= 0;
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b <= 0;
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c <= 0;
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end else if (rnd) begin
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a <= 0;
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b <= 0;
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end else begin
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{c, b, a} <= {c, b, a} + 3'b001;
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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rst = 0;
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rnd = 0;
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#1 rst = 1;
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#1 rst = 0;
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if ({c,b,a} !== 3'b000) begin
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$display("FAILED - no async reset");
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if ({c,b,a} !== 3'b001) begin
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$display("FAILED - First clock failed. {%b,%b,%b}", c, b, a);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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if ({c,b,a} !== 3'b101) begin
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$display("FAILED - Fifth clock failed. {%b,%b,%b}", c, b, a);
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$finish;
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end
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rnd = 1;
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#1 clk = 1;
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#1 clk = 0;
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if ({c,b,a} !== 3'b100) begin
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$display("FAILED - rnd failed. {%b,%b,%b}", c, b, a);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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