45 lines
791 B
Verilog
45 lines
791 B
Verilog
/*
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* This program tests the synthesis of small memories, including
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* aysnchronous read w/ synchronous write.
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*/
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module main;
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reg clk;
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reg Q, D;
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(* ivl_synthesys_on *)
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always @(negedge clk)
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Q <= D;
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(* ivl_synthesys_off *)
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initial begin
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clk = 1;
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D = 0;
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#2 clk = 0;
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#2 clk = 1;
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#2 if (Q !== 0) begin
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$display("FAILED -- initial setup D=%b, Q=%b", D, Q);
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$finish;
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end
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D = 1;
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#2 clk = 0;
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#2 if (Q !== 1) begin
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$display("FAILED -- negedge clk failed D=%b, Q=%b", D, Q);
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$finish;
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end
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D = 0;
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#2 clk = 1;
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#2 if (Q !== 1) begin
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$display("FAILED -- posedge clk tripped FF. D=%b, Q=%b", D, Q);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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