139 lines
3.1 KiB
Verilog
139 lines
3.1 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: deposit.v,v 1.4 2001/11/22 04:36:33 sib4 Exp $
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// Test for vpi_put_value() to properly propagate in structural context.
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module deposit_test;
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reg ck;
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reg start;
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initial start = 0;
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`ifdef RTL
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reg [3:0] cnt;
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wire cnt_tc = &cnt;
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always @(posedge ck)
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if (start | ~cnt_tc)
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cnt <= cnt + 1;
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`else // !ifdef RTL
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wire [3:0] cnt;
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wire [3:0] cnt_1;
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wire [3:0] cnt_c;
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wire cnt_tc;
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wire ne, e;
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and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]);
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not (ne, cnt_tc);
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or (e, ne, start);
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had A0 (cnt[0], 1'b1, cnt_c[0], cnt_1[0]);
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had A1 (cnt[1], cnt_c[0], cnt_c[1], cnt_1[1]);
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had A2 (cnt[2], cnt_c[1], cnt_c[2], cnt_1[2]);
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had A3 (cnt[3], cnt_c[2], cnt_c[3], cnt_1[3]);
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dffe C0 (ck, e, cnt_1[0], cnt[0]);
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dffe C1 (ck, e, cnt_1[1], cnt[1]);
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dffe C2 (ck, e, cnt_1[2], cnt[2]);
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dffe C3 (ck, e, cnt_1[3], cnt[3]);
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`endif // !ifdef RTL
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integer r0; initial r0 = 0;
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integer r1; initial r1 = 0;
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always
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begin
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#5 ck <= 0;
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#4;
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$display("%b %b %d %d", cnt, cnt_tc, r0, r1);
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if (cnt_tc === 1'b0) r0 = r0 + 1;
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if (cnt_tc === 1'b1) r1 = r1 + 1;
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#1 ck <= 1;
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end
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initial
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begin
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// $dumpfile("deposit.vcd");
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// $dumpvars(0, deposit_test);
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#22;
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`ifdef RTL
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cnt <= 4'b 1010;
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`else
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$deposit(C0.Q, 1'b0);
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$deposit(C1.Q, 1'b1);
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$deposit(C2.Q, 1'b0);
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$deposit(C3.Q, 1'b1);
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`endif
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#1 if (cnt !== 4'b1010)
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$display("FAILED");
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#99;
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$display("%d/%d", r0, r1);
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if (r0===5 && r1===5)
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$display("PASSED");
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else
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$display("FAILED");
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$finish;
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end
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endmodule
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`ifdef RTL
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`else
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module dffe (CK, E, D, Q);
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input CK, E, D;
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output Q;
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wire qq;
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UDP_dffe ff (qq, CK, E, D);
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buf #1 (Q, qq);
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endmodule
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primitive UDP_dffe (q, cp, e, d);
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output q;
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reg q;
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input cp, e, d;
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table
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(01) 1 1 : ? : 1 ;
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(01) 1 0 : ? : 0 ;
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* 0 ? : ? : - ;
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* ? 1 : 1 : - ;
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* ? 0 : 0 : - ;
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(1x) ? ? : ? : - ;
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(?0) ? ? : ? : - ;
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? ? * : ? : - ;
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? * ? : ? : - ;
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endtable
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endprimitive
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module had (A, B, C, S);
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input A, B;
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output C, S;
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xor s (S, A, B);
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and c (C, A, B);
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endmodule
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`endif // !ifdef RTL
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