74 lines
1.5 KiB
Verilog
74 lines
1.5 KiB
Verilog
/*
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* This program is derived from iverilog issue # 1327436.
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*/
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`timescale 1ns/1ns
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module verilog_test ();
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reg [24:0] APAD;
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wire [24:0] AIN;
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initial begin
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// $dumpfile("dumpfile.vcd");
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// $dumpvars;
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APAD=25'h1ffffff;
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#21 if (AIN !== APAD) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#79
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APAD=25'h1555555;
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#19 if (AIN !== 25'h1ffffff) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#2 if (AIN !== 25'h1555555) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#79
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APAD=25'h0aaaaaa;
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#19 if (AIN !== 25'h1555555) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#2 if (AIN !== 25'h0aaaaaa) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#79
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APAD=25'h1555555;
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#19 if (AIN !== 25'h0aaaaaa) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#2 if (AIN !== 25'h1555555) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#79
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APAD=25'h0aaaaaa;
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#19 if (AIN !== 25'h1555555) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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#2 if (AIN !== 25'h0aaaaaa) begin
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$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
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$finish;
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end
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$display("PASSED");
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end
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assign #20 AIN= APAD;
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endmodule
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