35 lines
1.0 KiB
Verilog
35 lines
1.0 KiB
Verilog
/*
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* Copyright (c) 1998 Philips Semiconductors (Stefan.Thiede@sv.sc.philips.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module test();
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MUX_REG_8x8 PAGE_REG_B3 (
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.CLK (CLK),
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/*
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.IN (DATA_RES[31:24]),
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.OUT (PAGE[31:24]),
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.EN_IN (EN_B3),
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.EN_OUT (PAGE_SEL),
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*/
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.TC (),
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.TD (),
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.TQ ());
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endmodule
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