68 lines
1.5 KiB
Verilog
68 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 1998 Philips Semiconductors (Stefan.Thiede@sv.sc.philips.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// 9/7/99 - SDW - Added a PASSED message - no functional checking needed
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module test();
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wire [1:0] a;
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wire [9:0] b;
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wire [0:9] d;
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a a1(.a(c));
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b b1(.a(a[0]));
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c ci(.a({a, b}));
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d d1(.a({d[0:9], a[1:0]}), .d(c));
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f f(a);
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a a3(a[1]);
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a a4({a[1]});
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g g({a,b});
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e e();
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initial
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$display("PASSED");
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endmodule
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module a(a);
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input a;
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endmodule
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module b(.a(b));
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input b;
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endmodule
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module c(.a({b, c}), );
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input [10:0] b;
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input c;
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endmodule
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module d(.a({b, c}), d);
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input [10:0] b;
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input c, d;
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endmodule
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module e();
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endmodule
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module f({a, b});
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input a, b;
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endmodule
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module g(a);
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input [11:0] a;
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endmodule
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