81 lines
1.3 KiB
Verilog
81 lines
1.3 KiB
Verilog
module main;
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reg [2:0] Q;
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reg clk, clr, up;
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(*ivl_synthesis_off *)
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initial begin
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clk = 0;
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up = 0;
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clr = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 0) begin
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$display("FAILED");
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$finish;
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end
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up = 1;
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clr = 0;
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#1 clk = 1;
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 3'b010) begin
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$display("FAILED");
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$finish;
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end
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up = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 3'b010) begin
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$display("FAILED");
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$finish;
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end
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clr = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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/*
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* This statement models a snythesizable UP counter. The up
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* count is enabled by the up signal. The clr is an asynchronous
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* clear input.
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*
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* NOTE: This is bad style. Bad, bad style. It comes from a
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* customer's customer, so I try to support it, but I'll moan
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* about it. Much better (and clearer) is:
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*
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* if (clr)
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* Q <= 0;
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* else
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* Q <= Q+1;
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*/
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(* ivl_synthesis_on *)
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always @(posedge clk, posedge clr) begin
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if (up)
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Q = Q + 1;
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if (clr)
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Q = 0;
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end
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endmodule // main
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