77 lines
2.1 KiB
Verilog
77 lines
2.1 KiB
Verilog
/*
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* Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* Test the ability to resolve resolve tri-state drivers onto a single
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* signal. Use multiple continuous assignments to a wire to create
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* multiple drivers, and use the ?: operator to tri-state the driven
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* value based on the sel value.
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*/
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module main;
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wire [1:0] out;
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reg [1:0] sel = 2'bzz;
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reg [1:0] v0 = 0;
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reg [1:0] v1 = 1;
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reg [1:0] v2 = 2;
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reg [1:0] v3 = 3;
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assign out = (sel == 2'b00)? v0 : 2'bz;
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assign out = (sel == 2'b01)? v1 : 2'bz;
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assign out = (sel == 2'b10)? v2 : 2'bz;
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assign out = (sel == 2'b11)? v3 : 2'bz;
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initial begin
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#1 if (out !== 2'bxx) begin
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$display("FAILED -- sel==%b, out==%b", sel, out);
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$finish;
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end
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sel = 0;
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#1 if (out !== 2'b00) begin
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$display("FAILED -- sel==%b, out==%b, v0==%b", sel, out, v0);
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$finish;
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end
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sel = 1;
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#1 if (out !== 2'b01) begin
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$display("FAILED -- sel==%b, out==%b", sel, out);
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$finish;
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end
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sel = 2;
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#1 if (out !== 2'b10) begin
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$display("FAILED -- sel==%b, out==%b", sel, out);
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$finish;
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end
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sel = 3;
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#1 if (out !== 2'b11) begin
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$display("FAILED -- sel==%b, out==%b", sel, out);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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