50 lines
673 B
Verilog
50 lines
673 B
Verilog
module mux(
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input wire [1:0] sel,
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input wire [2:0] i0,
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input wire [2:0] i1,
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input wire [2:0] i2,
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input wire [2:0] i3,
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input wire [2:0] i4,
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output reg [2:0] o
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);
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always @* begin
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case (sel)
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0 : o = i0;
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1 : o = i1;
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2 : o = i2;
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3 : o = i3;
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2 : o = i4;
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endcase
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end
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endmodule
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module test();
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reg [1:0] sel;
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wire [2:0] out;
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mux mux(sel, 3'd0, 3'd1, 3'd2, 3'd3, 3'd4, out);
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reg failed;
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(* ivl_synthesis_off *)
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initial begin
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failed = 0;
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sel = 0;
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repeat (4) begin
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#1 $display("%d : %b", sel, out);
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if (out !== sel) failed = 1;
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sel = sel + 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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