33 lines
524 B
Verilog
33 lines
524 B
Verilog
module main;
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reg [3:0] cond;
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reg [2:0] t;
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always @*
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case (cond&4'b1110)
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'h0: t = 7;
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'h2: t = 6;
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'h4: t = 5;
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'h6: t = 4;
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'h8: t = 3;
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'ha: t = 2;
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'hc: t = 1;
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'he: t = 0;
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endcase
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integer i;
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initial begin
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for (i = 0 ; i < 8 ; i = i + 1) begin
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cond = i << 1;
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#1 if (t !== (7 - i)) begin
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$display("FAILED -- i=%d, cond=%b, t=%b", i, cond, t);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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